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VHDL Shift Register

Posted by in on 2-6-13

Shift registers are a fundamental part of nearly every FPGA design, allowing the ability to delay the flow of data and examine previous values in the architecture pipeline.

This article will cover the following concepts:

  1. Shift Register Concepts
  2. VHDL Implementation
  3. Synthesis Considerations
  4. Typical Uses

For a Verilog shift register, see our corresponding shift register article with example code and Verilog specific tips.


Shift Register Concepts

A shift register is a series of connected registers (flip-flops) that are sequentially connected together so that a value at the input is passed from one register to the next on each clock cycle. In some designs, every register element can be accessed individually, while other implementations only allow access at specific locations. An illustration of a shift register is shown below, where data is entering the register chain at the least significant bit (LSB), or the right side of the picture.

Shift Register

The above illustration shows a single-bit wide shift register with a length of 8, but there is nothing special about those numbers. Depending on the implementation method (code or IP), any practical dimensions can be used.

A single-bit shift register can be implemented in VHDL using the std_logic_vector construct. If you want to shift multiple bits at a time (e.g. a byte, word, double word, etc.), the shift register must use a custom type defined by you. The custom type needed to form the multi-bit width shift register is simply an array of the std_logic_vector construct. An 8-bit wide shift register that is 32 bytes in length uses this custom signal type:
[cc lang=”vhdl” noborder=”true” tab_size=”4″ lines=”-1″ width=”600″ escaped=”true”]
type sr32x8 is array (0 to 31) of std_logic_vector(7 downto 0);
signal shift_reg : sr32x8; construct.

The code example implements both a single- and multi-bit shift register.


VHDL Shift Register Code

[cc lang=”vhdl” noborder=”true” tab_size=”4″ lines=”-1″ width=”600″ escaped=”true”]
entity shift_register is
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic;
BIT_OUT : out std_logic;
BYTE_OUT : out std_logic_vector(7 downto 0)
end shift_register;

architecture bhv of shift_register is

— signal definitions

–shift register signals
type sr12x8 is array (0 to 11) of std_logic_vector(7 downto 0);
signal bit_shift_reg : std_logic_vector(7 downto 0);
signal byte_shift_reg : sr12x8;


— shift register

–shift register
if(rising_edge(CLK)) then

–intitialize shift registers to zero on reset
if(RST=’1′) then
bit_shift_reg <= (others=>‘0’);
byte_shift_reg <= (others=>(others=>’0′));

–bit shift register
bit_shift_reg(7 downto 1) <= bit_shift_reg(6 downto 0); bit_shift_reg(0) <= DATA_IN; --byte shift register byte_shift_reg(1 to 11) <= byte_shift_reg(0 to 10); byte_shift_reg(0) <= bit_shift_reg; end if; end if; end process; ---------------------------------------------------------------- -- outputs ---------------------------------------------------------------- --module output registers process(RST,CLK) begin if(rising_edge(CLK)) then if(RST='1') then BIT_OUT <= '0'; BYTE_OUT <= (others=>‘0’);
BIT_OUT <= bit_shift_reg(7); BYTE_OUT <= byte_shift_reg(11); end if; end if; end process; end bhv; [/cc]  

Synthesis Considerations

Seemingly small differences in VHDL code will produce different results when implemented inside a real FPGA. One of the most important is how you reset the shift register–applying a reset to all the registers (as shown in the example) or only the first register.

Using a reset on the entire register bank will potentially cause an increase in resource utilization in the FPGA. Since some architectures only support a single reset line for a group of flip-flops, forcing each register to reset may cause only one flip-flop in a group to be utilized, stretching the design across several configurable logic blocks (CLBs). In many FPGAs, a more compact design is synthesized when the reset only needs to be applied to one register element.

Other coding considerations involve ensuring that the size of your shift register is appropriate for the targeted block RAM (BRAM) in the FPGA. Matching the width of a BRAM, for instance, can go a long way to allowing the design to run at the highest speed.

Besides manually coding the shift register in VHDL, you may choose to use built-in cores from the manufacturer that optimize the design according to the architecture of the specific FPGA (Xilinx calls these IPCores). I typically code the shift register in VHDL if the length will be short and I will need data from multiple delays. If only one tap is needed, or the shift register needs to be fairly long, I will use the IPCore.


Typical Uses

Shift registers are used whenever you’d like to delay the data signal by one or more clock cycles so that you can use it later–either for a data operation or output. One common example would be to equalize the delay of two parallel signals–possibly a data and a data valid indicator. Often a data valid indicator is delayed to match the latency of operations performed on the data stream.

Happy coding!

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