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Verilog Shift Register

Posted by in on 2-12-13

Shift registers are a fundamental part of nearly every FPGA design, allowing the ability to delay the flow of data and examine previous values in the architecture pipeline.

This article will cover the following concepts:

  1. Shift Register Concepts
  2. Verilog Implementation
  3. Synthesis Considerations
  4. Typical Uses

For a VHDL shift register, see our corresponding shift register article with example code and VHDL specific tips.


Shift Register Concepts

A shift register is a series of connected registers (flip-flops) that are sequentially connected together so that a value at the input is passed from one register to the next on each clock cycle. In some designs, every register element can be accessed individually, while other implementations only allow access at specific locations. An illustration of a shift register is shown below, where data is entering the register chain at the least significant bit (LSB), or the right side of the picture.

Shift Register

The above illustration shows a single-bit wide shift register with a length of 8, but there is nothing special about those numbers. Depending on the implementation method (code or IP), any practical dimensions can be used.

A single-bit shift register can be implemented in Verilog using concatenation. If you want to shift multiple bits at a time (e.g. a byte, word, double word, etc.), the shift register must use a for loop. This is because Verilog does not allow bulk addressing of memory types, which is how Verilog classifies two dimensional arrays.

The code example implements both a single- and multi-bit shift register.


Verilog Shift Register Code

[cc lang=”verilog” noborder=”true” tab_size=”4″ lines=”-1″ width=”600″ escaped=”true”]
module shift_register_v(
input CLK,
input RST,
input DATA_IN,
output BIT_OUT,
output [7:0] BYTE_OUT

// signal definitions

//shift register signals
reg [7:0] bitShiftReg;
reg [7:0] byteShiftReg[11:0];
integer i;

// shift register

//shift register
always @(posedge CLK)

//bit shift register
bitShiftReg <= {bitShiftReg[6:0],DATA_IN};

//byte shift register
byteShiftReg[0] <= bitShiftReg;
byteShiftReg[i] <= byteShiftReg[i-1];

// outputs

//module output wires
assign BIT_OUT = bitShiftReg[7];
assign BYTE_OUT = byteShiftReg[11];


Synthesis Considerations

Seemingly small differences in Verilog code will produce different results when implemented inside a real FPGA. One of the most important is how you reset the shift register–applying a reset to all the registers (as shown in the example) or only the first register.

Using a reset on the entire register bank will potentially cause an increase in resource utilization in the FPGA. Since some architectures only support a single reset line for a group of flip-flops, forcing each register to reset may cause only one flip-flop in a group to be utilized, stretching the design across several configurable logic blocks (CLBs). In many FPGAs, a more compact design is synthesized when the reset only needs to be applied to one register element.

Other coding considerations involve ensuring that the size of your shift register is appropriate for the targeted block RAM (BRAM) in the FPGA. Matching the width of a BRAM, for instance, can go a long way to allowing the design to run at the highest speed.

Besides manually coding the shift register in Verilog, you may choose to use built-in cores from the manufacturer that optimize the design according to the architecture of the specific FPGA (Xilinx calls these IPCores). I typically code the shift register in Verilog if the length will be short and I will need data from multiple delays. If only one tap is needed, or the shift register needs to be fairly long, I will use the IPCore.


Typical Uses

Shift registers are used whenever you’d like to delay the data signal by one or more clock cycles so that you can use it later–either for a data operation or output. One common example would be to equalize the delay of two parallel signals–possibly a data and a data valid indicator. Often a data valid indicator is delayed to match the latency of operations performed on the data stream.


More Resources

If you’re new to Verilog coding, it’s often helpful to simply read through a good text book on the subject.  My favorite book on Verilog is Verilog HDL by Samir Palnitkar.  This book covers great detail of how to approach designs in Verilog, from basic syntax to implementation examples.  The book does have a slant towards simulation at the beginning, but the chapter on synthesis constraints round out the material nicely.  This is my go-to book for Verilog.


Happy coding!

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