Any given VHDL FPGA design may have multiple VHDL types being used. The most common VHDL types used in synthesizable VHDL code are std_logic, std_logic_vector, signed, unsigned, and integer. Because VHDL is a strongly-typed language, most often differing types cannot be used in the same expression. In cases where you can directly combine two types into one expression, you are really leaving it up to the compiler or synthesis tool to determine how the expression should behave, which is a...
Read More
Counters are a principle part of nearly every FPGA design, facilitating time tracking in logic circuits by counting clock cycles. I’m going to discuss VHDL counter construction, and I also want to share a very practical counter tip that I picked up from a colleague many years back: count backwards.
This article will cover the following concepts:
Counter Concepts
VHDL Implementation
Synthesis Considerations
Typical Uses
For a Verilog counter, see our corresponding counter article with...
Read More
Shift registers are a fundamental part of nearly every FPGA design, allowing the ability to delay the flow of data and examine previous values in the architecture pipeline.
This article will cover the following concepts:
Shift Register Concepts
VHDL Implementation
Synthesis Considerations
Typical Uses
For a Verilog shift register, see our corresponding shift register article with example code and Verilog specific tips.
Shift Register Concepts
A shift register is a series of connected...
Read More
If you want to be an FPGA programmer, which of the two dominant FPGA programming languages do you learn? This question is asked so often by engineers new to the field of digital design, you’d think there would be a definitive answer. In this article I’m going to cover the main differences, pros, and cons about each language, but first I’m going to tell you that you’re asking the wrong question.
The Right Question
The wrong question is, “which language should I learn?”....
Read More
Recent Comments