Verilog vs. VHDL
If you want to be an FPGA programmer, which of the two dominant FPGA programming languages do you learn? This question is asked so often by engineers new to the field of digital design, you’d think there would be a definitive answer. In this article I’m going to cover the main differences, pros, and cons about each language, but first I’m going to tell you that you’re asking the wrong question.
The Right Question
The wrong question is, “which language should I learn?”. The better question is, “which language should I learn first?”. Surprisingly, it really doesn’t matter which language you learn now, because you’re going to end up working with both. It’s not as scary as it sounds!
Learning Verilog after VHDL (or vice versa) is like getting into shape by running and then switching to cycling after a few months. Either sport will get you into shape, and while the muscle groups you use in the two sports aren’t exactly the same, both activities will make your heart strong enough for either of the sports. Likewise, the concepts you learn in VHDL will transfer easily to Verilog, or the other way around. Don’t get caught up thinking that you’re pinning your FPGA programming career down to one language.
Choose the Language That Suits Your Needs
To answer the question of VHDL vs Verilog, you should really keep in mind your goals and where you’ll be using the language. In the United States, the commercial industries tend to use more Verilog, while the aerospace and defense industries more heavily favor VHDL; the language you learn should reflect which industry you’re more interested in.
Also consider the depth and style you’re comfortable working at. VHDL lends itself to describing hardware at more abstracted levels (like case statements, if/then, etc.), while Verilog is good at describing hardware down to the gate level (nand, xor, etc.). If you’re not familiar with schematic layout or your background is heavy in computer programming, you might be better off using VHDL until you really get familiar with the physical FPGA constructs.
VHDL: A Great Learning Language
If you have no language inclination either way, then my recommendation is VHDL. VHDL is a strongly-typed language, so syntax errors are found more easily by the compiler instead of manually combing through the code looking for an improper usage that is causing problems.
Verilog is somewhat more flexible, but the syntax rules will let you create circuit connections you probably didn’t intend to make, and some of the syntax nuances are confusing for a beginner (wire vs reg). Many engineers who learn Verilog first say that crossing to VHDL was difficult, while I’ve never heard that from the opposite view.
If you have guidance while you learn your first language, like an experienced colleague to help you learn and bounce questions off, then my prefered language is Verilog.
Comparison and Contrast
Beyond considerations for learning your first language, both languages have their advantages and disadvantages.
- Strongly typed language.
- Dealing with signed and unsigned numbers is natural, and there’s less chance of making a precision mistake or assigning a 16-bit signal to a 4-bit signal.
- Ability to define custom types.
- A VHDL state machine can be coded naturally using the actual state names (e.g. wait, acknowledge, transmit, receive, etc.), not binary state numbers (e.g. 00, 01, 10, 11).
- Record types.
- Define multiple signals into one type.
- Natural coding style for asynchronous resets.
- Easily reverse bit order of a word.
- Logical statement (like case and if/then) endings are clearly marked.
- Extremely verbose coding.
- VHDL modules must be defined by a prototype and declared before they’re used, causing you to change code in at least 3 places if you want to make a change to the interface.
- The use of the keyword “downto” in every bit vector definition is tedious.
- Sensitivity lists.
- Missing a single signal in the sensitivity list can cause catastrophic differences between simulation and synthesis.
- Each process must have a sensitivity list that may sometimes be very long.
- Type conversions.
- Signal types that are clearly related (e.g. std_logic and std_logic_vector) cannot be simply used together and must be converted to another type.
- Compact language.
- Small code footprint.
- Familiar language conventions similar to C.
- Mixing and matching signals is very easy.
- Reduction operators.
- Perform logical tests on an entire array of bits with a single operator.
- Low-level descriptions closer to actual hardware.
- Instantiate gates directly.
- Explicitly declare wires and registers directly.
- Compiler directives.
- Weakly-typed language.
- Code is more error prone due to accidental combination of differing signal types.
- Possible to create signal with a typo.
- No sensitivity lists.
- Less of a chance of design synthesis and simulation problems arising from coding.
- No support of custom types.
- State machine coding is more difficult because states must be numeric values with a static bit widths (techniques exist to ease this problem).
- Confusing signal declarations.
- Signal declarations are not always required.
- The difference between a wire and reg is not always obvious for beginners, and a reg can sometimes be a wire.
- Confusing language conventions for beginners.
- The difference between blocking and non-blocking statements is sometimes difficult to grasp for beginning FPGA programmers.
- Reduced support for asynchronous signals.
- Using asynchronous signals slows down simulation software.
- Language constructs don’t support natural usage of asynchronous signals.
One additional consideration for Verilog is that System Verilog is beginning to be used more, but mostly for FPGA design verification.
Coca-Cola or Pepsi?
In the end, it really comes down to your preferences. Engineers on both sides of the debate are sometimes fanatical, but the choice is like choosing Coca-Cola or Pepsi.
Either language is fully capable of implementing demanding FPGA programs. I prefer Verilog because it’s quicker to code, but go back to VHDL to do most of my state machine designs. I’ve hired a number of engineers for FPGA jobs, and I’ve never considered knowing one language or the other a deal-breaker. It’s more important that concepts are understood, and either language will facilitate that.
If you’re looking to learn either language, there are two “go-to” books for learning hardware description language (HDL). For VHDL, I recommend The Designer’s Guide to VHDL by Peter Ashenden. For Verilog, I recommend Verilog HDL by Samir Palnitkar.
Which language do you prefer and why? Did I miss any big advantage or disadvantage? Let me know!