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Creating a New Design in Xilinx System Generator and the Xilinx Blockset

Posted by in on 5-12-13

The Xilinx System Generator design flow is a fantastic tool for implementing digtial signal processing (DSP) designs in Xilinx FPGAs.

This video series will introduce Xilinx System Generator and cover the basic principles of the design flow.  The video will also contrast the System Generator design flow with typical HDL-only design flow.

The full video series (still under development) consists of several parts:

  1. Introduction
  2. Creating a New Design and the Xilinx Blockset
  3. Designing DSP Algorithms for FPGAs with the Xilinx Blockset
  4. Driving FPGA Designs with Simulink Sources
  5. Capturing End and Intermediate Results Using the Wave Scope Block
  6. Capturing End and Intermediate Results Using the MATLAB Environment
  7. Examining Timing Performance
  8. Generating Implementation Files
  9. Setting Up a Hardware Co-Simulation using a Xilinx Development Board
  10. Communicating Data Between the MATLAB Environment and a Hardware Co-Simulation
  11. Opening a Design for Hardware Co-Simulation
  12. Running a Design in Hardware Co-Simulation

The video outline is located below the video.

 

  • Overview

    • Creating a new design using MATLAB Simulink

    • Tour of the Xilinx block set for Simulink

  • Creating a New Design Using MATLAB Simulink

    • Open up the design environment using the Xilinx shortcut

      • Don’t start MATLAB directly.

    • Create new MDL file

    • Change preferences to discrete, fixed-step simulator

  • Xilinx Block Set for Simulink

    • Every System Generator design must contain a System Generator tolken

    • Almost every design will need in and out gateways.

    • Tour of Xilinx Blocksets

 

 

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