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Verilog Counter

Posted in on 2-12-13

Verilog Counter

Counters are a principle part of nearly every FPGA design, facilitating time tracking in logic circuits by counting clock cycles. I’m going to discuss Verilog counter construction, and I...

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Verilog Shift Register

Posted in on 2-12-13

Verilog Shift Register

Shift registers are a fundamental part of nearly every FPGA design, allowing the ability to delay the flow of data and examine previous values in the architecture pipeline. This article...

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VHDL Type Conversion

Posted in on 2-10-13

VHDL Type Conversion

Any given VHDL FPGA design may have multiple VHDL types being used. The most common VHDL types used in synthesizable VHDL code are std_logic, std_logic_vector, signed, unsigned, and...

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VHDL Counter

Posted in on 2-10-13

VHDL Counter

Counters are a principle part of nearly every FPGA design, facilitating time tracking in logic circuits by counting clock cycles. I’m going to discuss VHDL counter construction, and I...

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VHDL Shift Register

Posted in on 2-6-13

VHDL Shift Register

Shift registers are a fundamental part of nearly every FPGA design, allowing the ability to delay the flow of data and examine previous values in the architecture pipeline. This article...

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Verilog vs. VHDL

Posted in on 2-4-13

Verilog vs. VHDL

If you want to be an FPGA programmer, which of the two dominant FPGA programming languages do you learn?  This question is asked so often by engineers new to the field of digital design,...

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